NT5CC128M16IP-DI DRAM Chip DDR3L SDRAM 2Gbit 128Mx16 1.35V 96-Pin VFBGA
属性
制造商 NANYA
Lead Time 3(168 Hours)
存储器类型 DRAM Chip DDR3L SDRAM
存储器框架 128Mx16
Density 2Gb
Interface And Power SSTL_135 (1.35V, 1.35V) / SSTL-15(1.35V, 1.35V)
Nanya Designator NT
Grade Commercial Grade
脚位/封装 FBGA-96
外包装 TRAY
无铅/环保 无铅/环保
电压(伏) 1.35v
温度规格 0°C~+95°C
速度 800 MHZ
Descriptions
The 2Gb Double-Data-Rate-3 (DDR3(L)) isdouble data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAMs. The 2Gb chip is organized as32Mbit x 8 I/Os x 8 banks or 16Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1866Mb/sec/pin for general applications.The chip is designed to comply with all key DDR3(L)DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CKfalling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V or 1.35V -0.067V/+0.1Vpower supply and are available in BGA packages.
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