MT40A512M16JY-083E:B DDR4 原装
DDR4 SDRAM 8G 512MX16 FBGA
DDR4 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally configured as an 16-bank (4-banks per Bank Group) DRAM
MT40A512M16JY-083E:B DDR4 原装的技术参数：
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制造商: |
Micron Technology |
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产品种类: |
动态随机存取存储器 |
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RoHS: |
是 |
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类型: |
SDRAM - DDR4 |
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安装风格: |
SMD/SMT |
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封装 / 箱体: |
FBGA-96 |
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数据总线宽度: |
16 bit |
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组织: |
512 M x 16 |
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存储容量: |
8 Gbit |
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（max）时钟频率: |
1.2 GHz |
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电源电压: |
1.14 V ~ 1.26 V |
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电源电流（max）: |
100 mA |
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工作温度: |
0 C ~+ 95 C |
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封装: |
Reel |
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封装: |
Cut Tape |
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工厂包装数量: |
2000 |
MT40A512M16JY-083E:B DDR4 原装的描述：
The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen banks (4 bank groups with 4 banks for each bank group) for x4/x8 devices, and as eight banks for each bank group (2 bank groups with 4 banks each) for x16 devices.
The device uses double data rate (DDR) architecture to achieve high-speed operation. DDR4 architecture is essentially an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for a device module effectively consists of a single 8n-bit-wide, four-clockcycle-data transfer at the internal DRAM core and eight corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins.
Read and write accesses to the device are burst-oriented. Accesses start at a selected location and continue for a burst length of eight or a chopped burst of four in a programmed sequence.
Operation begins with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.
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