K4A8G085WB-BCRC 原装 DDR4
8Gb B-die DDR4 SDRAM 78FBGA with Lead-Free & Halogen-Free (RoHS compliant) 1.2V
K4A8G085WB-BCRC 原装 DDR4 的技术参数：
|
制造商 |
Samsung |
|
产品类型 |
DDR4 SDRAM |
|
容量 (bit) |
8G (1G x 8 ) |
|
位数/字（位） |
8 |
|
数据总线宽度（位） |
8 |
|
（max）时钟频率 (MHz) |
2400 |
|
（max）访问时间 (ns) |
0.175 |
|
地址总线宽度（位） |
18 |
|
接口类型 |
POD |
|
工作电源电压 (V) |
1.14 to 1.26 |
|
典型工作电源电压 (V) |
1.2 |
|
工作温度 (°C) |
0 to 85 |
|
I/O 线数（位） |
8 |
|
封装 |
FBGA-78 |
|
安装 |
表面贴装 |
K4A8G085WB-BCRC 原装 DDR4 的技术参数：
The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks, 4 bank group with 4 banks for each bank group for x4/x8 and eight-banks, 2 bank group with 4 banks for each bankgroup for x16 DRAM.
The DDR4 SDRAM uses a 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.
The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode ‘on the fly’ (via A12) if enabled in the mode register.
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